Current source and drain arrangement for magnetoresistive memories (MRAMS)

An MRAM device (400) having write paths with substantially uniform length and resistance for all memory cells within the memory array (411). CVC circuits are positioned with respect to the memory array (411) such that the write path length along conductive lines of the MRAM device (401) is substantially the same for all memory cells in the array (411), ensuring that the resistance along the write path is substantially uniform, and therefore, the amount of write current provided by the CVC circuits to write the cells of the memory array (411) is substantially the same.