High speed VLSI digital tester architecture for real-time output timing acquisition, results accumulation, and analysis

A tester for testing a digital device. The tester includes a plurality of time measurement units to measure transition timing values of output data of each output pin of the digital device in each test cycle. A plurality of result operations units performs real-time arithmetic operations on the measured transition timing values to produce a pass/fail result and additional test results. A plurality of result accumulators stores the pass/fail result and a number of selected test results. And a capture/analysis engine captures and analyzes the pass/fail result and the selected results to provide comprehensive test performance of the digital device.