Ground via structures in semiconductor packages

Ground via structures in semiconductor packages

A package for a semiconductor chip is provided. The package includes a ground conducting layer. A one metal layer interconnect substrate is attached to the ground conducting layer. The one metal layer interconnect substrate includes a via hole defining a path to the ground conducting layer. A conduc...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: RYU SEUNG RYUL, SOHN JU YUNG
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A package for a semiconductor chip is provided. The package includes a ground conducting layer. A one metal layer interconnect substrate is attached to the ground conducting layer. The one metal layer interconnect substrate includes a via hole defining a path to the ground conducting layer. A conductive material substantially filling the path defined by the via hole is provided. The conductive material is in contact with the ground conducting layer.