Microprocessor memory device controller

A memory manager which is capable of modifying microprocessor memory access signals to selectively control access to memory devices as a series of memory banks. Memory bank control registers are associated with each memory bank for retaining interface parameters utilized by the memory manager to control memory access signal generation for each memory bank. By way of example, the memory bank control register allows the selection of wait states, access signal generation, write protection, and page-mode addressing as a result of selective address signal inversion. The memory manager may be implemented within a microprocessor, or integrated within a separate circuit.