SEMICONDUCTOR CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME

A semiconductor package includes: a substrate having conductive lead patterns formed on a bottom surface of the substrate; a semiconductor chip electrically connected to the substrate by bonding wires or bumps and flip-chip bonding; and an encapsulating body that encapsulates the semiconductor chip....

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: SUNG SIAN, KIM JAE-HONG
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:A semiconductor package includes: a substrate having conductive lead patterns formed on a bottom surface of the substrate; a semiconductor chip electrically connected to the substrate by bonding wires or bumps and flip-chip bonding; and an encapsulating body that encapsulates the semiconductor chip. The semiconductor package can further include a deformation preventing pattern that is under the semiconductor chip to reduce warpage of the package. In accordance with another embodiment of the invention, a method for forming the semiconductor package includes: preparing the substrate; electrically connecting the chip to the conductive pattern; and encapsulating semiconductor chip. The packages and manufacturing methods in accordance with the present invention employ common packaging components and processes to avoid the extra cost and difficulties associated with conventional fine-pitch plastic packages.