SYSTEM AND METHOD FOR CONCURRENT PLACEMENT OF GATES AND ASSOCIATED WIRING

SYSTEM AND METHOD FOR CONCURRENT PLACEMENT OF GATES AND ASSOCIATED WIRING

A design tool for integrated circuits includes a placement tool which places logic gates and interconnect components concurrently. Probabilistic interconnect models are used to represent the collection of possible interconnect routings that provide acceptable circuit performance and routing area.

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Bibliographische Detailangaben
Hauptverfasser: YEAP GARY K, TARAPOREVALA FEROZE PESHOTAN, SARRAFZADEH MAJID, PILEGGI LAWRENCE, GAO TONG, BOYLE DOUGLAS B
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A design tool for integrated circuits includes a placement tool which places logic gates and interconnect components concurrently. Probabilistic interconnect models are used to represent the collection of possible interconnect routings that provide acceptable circuit performance and routing area.