Integrated circuit and method of manufacturing same

An integrated circuit arrangement having two NMOS transistors with different cut off voltages and two PMOS transistors with different cut off voltages. Channel regions of the NMOS transistors exhibit the same dopant concentration. The analogous case applies to the PMOS transistors. The different cut...

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Bibliographische Detailangaben
Hauptverfasser: LUSTIG BERNHARD, FRANOSCH MARTIN
Format: Patent
Sprache:eng
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Zusammenfassung:An integrated circuit arrangement having two NMOS transistors with different cut off voltages and two PMOS transistors with different cut off voltages. Channel regions of the NMOS transistors exhibit the same dopant concentration. The analogous case applies to the PMOS transistors. The different cut off voltages are achieved by different chemical compositions of the gate electrodes of the transistors. Preferably, the chemical compositions of the gate electrodes of respectively one of the NMOS transistors and one of the PMOS transistors thereby coincide. Si1-xGex with 0