Processing elements array that includes delay queues between processing elements to hold shared data
A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processin...
Gespeichert in:
| Hauptverfasser: | , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Yen, Yu-Xiang Hsieh, Wan-Shan Liou, Jing-Jia Huang, Chih-Tsun Chen, Yao-Hua Lu, Juin-Ming |
| description | A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processing element perform the convolution according to a shared datum at least. The delayed queue circuit connects to the first processing element and connects to the second processing element. The delayed queue circuit receives the shared datum sent by the first processing element, and sends the shared datum to the second processing element after receiving the shared datum and waiting for a time interval. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US12190224B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US12190224B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US12190224B23</originalsourceid><addsrcrecordid>eNqNizEKAjEQRbexEPUO4wEEN9rYKoqloNbLuPluFmISMxPE27uFpYXV5z3eH1f2lGMLkT50BI8HggpxzvwmdazUh9YXCyELP7hnQRngBn0BgdKPs0Zy0VsSxxmWLCtPq9GdvWD23Uk1P-wvu-MCKTaQxC0CtLmea1Nvlsast2b1T_MBPMQ_cA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Processing elements array that includes delay queues between processing elements to hold shared data</title><source>esp@cenet</source><creator>Yen, Yu-Xiang ; Hsieh, Wan-Shan ; Liou, Jing-Jia ; Huang, Chih-Tsun ; Chen, Yao-Hua ; Lu, Juin-Ming</creator><creatorcontrib>Yen, Yu-Xiang ; Hsieh, Wan-Shan ; Liou, Jing-Jia ; Huang, Chih-Tsun ; Chen, Yao-Hua ; Lu, Juin-Ming</creatorcontrib><description>A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processing element perform the convolution according to a shared datum at least. The delayed queue circuit connects to the first processing element and connects to the second processing element. The delayed queue circuit receives the shared datum sent by the first processing element, and sends the shared datum to the second processing element after receiving the shared datum and waiting for a time interval.</description><language>eng</language><subject>CALCULATING ; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2025</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20250107&DB=EPODOC&CC=US&NR=12190224B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20250107&DB=EPODOC&CC=US&NR=12190224B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Yen, Yu-Xiang</creatorcontrib><creatorcontrib>Hsieh, Wan-Shan</creatorcontrib><creatorcontrib>Liou, Jing-Jia</creatorcontrib><creatorcontrib>Huang, Chih-Tsun</creatorcontrib><creatorcontrib>Chen, Yao-Hua</creatorcontrib><creatorcontrib>Lu, Juin-Ming</creatorcontrib><title>Processing elements array that includes delay queues between processing elements to hold shared data</title><description>A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processing element perform the convolution according to a shared datum at least. The delayed queue circuit connects to the first processing element and connects to the second processing element. The delayed queue circuit receives the shared datum sent by the first processing element, and sends the shared datum to the second processing element after receiving the shared datum and waiting for a time interval.</description><subject>CALCULATING</subject><subject>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2025</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNizEKAjEQRbexEPUO4wEEN9rYKoqloNbLuPluFmISMxPE27uFpYXV5z3eH1f2lGMLkT50BI8HggpxzvwmdazUh9YXCyELP7hnQRngBn0BgdKPs0Zy0VsSxxmWLCtPq9GdvWD23Uk1P-wvu-MCKTaQxC0CtLmea1Nvlsast2b1T_MBPMQ_cA</recordid><startdate>20250107</startdate><enddate>20250107</enddate><creator>Yen, Yu-Xiang</creator><creator>Hsieh, Wan-Shan</creator><creator>Liou, Jing-Jia</creator><creator>Huang, Chih-Tsun</creator><creator>Chen, Yao-Hua</creator><creator>Lu, Juin-Ming</creator><scope>EVB</scope></search><sort><creationdate>20250107</creationdate><title>Processing elements array that includes delay queues between processing elements to hold shared data</title><author>Yen, Yu-Xiang ; Hsieh, Wan-Shan ; Liou, Jing-Jia ; Huang, Chih-Tsun ; Chen, Yao-Hua ; Lu, Juin-Ming</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12190224B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2025</creationdate><topic>CALCULATING</topic><topic>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Yen, Yu-Xiang</creatorcontrib><creatorcontrib>Hsieh, Wan-Shan</creatorcontrib><creatorcontrib>Liou, Jing-Jia</creatorcontrib><creatorcontrib>Huang, Chih-Tsun</creatorcontrib><creatorcontrib>Chen, Yao-Hua</creatorcontrib><creatorcontrib>Lu, Juin-Ming</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yen, Yu-Xiang</au><au>Hsieh, Wan-Shan</au><au>Liou, Jing-Jia</au><au>Huang, Chih-Tsun</au><au>Chen, Yao-Hua</au><au>Lu, Juin-Ming</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Processing elements array that includes delay queues between processing elements to hold shared data</title><date>2025-01-07</date><risdate>2025</risdate><abstract>A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processing element perform the convolution according to a shared datum at least. The delayed queue circuit connects to the first processing element and connects to the second processing element. The delayed queue circuit receives the shared datum sent by the first processing element, and sends the shared datum to the second processing element after receiving the shared datum and waiting for a time interval.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US12190224B2 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Processing elements array that includes delay queues between processing elements to hold shared data |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T15%3A28%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Yen,%20Yu-Xiang&rft.date=2025-01-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS12190224B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |