Processing elements array that includes delay queues between processing elements to hold shared data

Processing elements array that includes delay queues between processing elements to hold shared data

A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processin...

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Bibliographische Detailangaben
Hauptverfasser: Yen, Yu-Xiang, Hsieh, Wan-Shan, Liou, Jing-Jia, Huang, Chih-Tsun, Chen, Yao-Hua, Lu, Juin-Ming
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Zusammenfassung:A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processing element perform the convolution according to a shared datum at least. The delayed queue circuit connects to the first processing element and connects to the second processing element. The delayed queue circuit receives the shared datum sent by the first processing element, and sends the shared datum to the second processing element after receiving the shared datum and waiting for a time interval.