Memory cell array with row direction gap between erase gate lines and dummy floating gates

A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Lemke, Steven, Kim, Jinho, Liu, Xian, Om'Mani, Henry A, Schneider, Louisa, Tran, Hieu Van, Ghazavi, Parviz, Do, Nhan
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES
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