Detecting data bus drive faults

Methods, systems, and devices for memory operations are described. A pin associated with communicating error correction information may be biased, via a first circuit, to a first voltage level by a first voltage source that is coupled with the pin when the pin is in an idle state. Also, a set of data pins may be biased, via a second circuit, to a second voltage level by a second voltage source when the set of data pins is in the idle state. When a memory device misses a command transmitted from a host device, the voltage levels of the pin and set of data pins may remain at the respective voltage levels throughout a period during which the host device executes an operation associated with the missed command, indicating to the host device that data communicated by a corresponding data signal is invalid.