Lossless tiling in convolution networks-resetting overlap factor to zero at section boundaries

A data processing system includes compile time logic to section a graph into a sequence of sections, including a first section followed by a second section. The compile time logic configured the first section to generate a first output in a first non-overlapping target configuration in response to p...

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Hauptverfasser: Chaphekar, Ruddhi, Sivaramakrishnan, Ram, Musaddiq, Matheen, Prabhakar, Raghu, Fuchs, Adi, Wang, Junjue, Sujeeth, Arvind Krishna, Jairath, Sumti, Nama, Tejas Nagendra Babu, Liang, Kaizhao
Format: Patent
Sprache:eng
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Zusammenfassung:A data processing system includes compile time logic to section a graph into a sequence of sections, including a first section followed by a second section. The compile time logic configured the first section to generate a first output in a first non-overlapping target configuration in response to processing an input in a first overlapping input configuration, and configures the second section to generate a second output in a second non-overlapping target configuration in response to processing the first output in a second overlapping input configuration. The compile time logic also creates a set of computer instructions to execute the first section and the second section on a target processing system.