Semiconductor package and method of fabricating the same

Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconduc...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Han, Cheolsoo, Jung, Sanghoon, Kim, Young Lyong
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate.