Scalable neural network accelerator architecture

Scalable neural network accelerator architecture

A scalable neural network accelerator may include a first circuit for selecting a sub array of an array of registers, wherein the sub array comprises LH rows of registers and LW columns of registers, and wherein LH and RH are integers. The accelerator may also include a register for storing a value...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Widdershoven, Franciscus Petrus, Kimelman, Paul, Kahne, Brian Christopher, Lu, Xiaomin, Fuks, Adam
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
PHYSICS
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Beschreibung
Zusammenfassung:A scalable neural network accelerator may include a first circuit for selecting a sub array of an array of registers, wherein the sub array comprises LH rows of registers and LW columns of registers, and wherein LH and RH are integers. The accelerator may also include a register for storing a value that determines LH. In addition, the accelerator may include a first load circuit for loading data received from the memory bus into registers of the sub array.