Graphics processor operation scheduling for deterministic latency

Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to di...

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Bibliographische Detailangaben
Hauptverfasser:	K, Pattabhiraman, Ould-Ahmed-Vall, Elmoustapha, S, Jayakrishna P, Tangri, Saurabh, George, Varghese, Panneer, Selvakumar, Jain, Nilesh, Samson, Eric, Iyer, Ravishankar, Koker, Altug, Ray, Joydeep, Ashbaugh, Ben, Mastronarde, Josh, MacPherson, Mike, Appu, Abhishek, Janus, Scott
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING CODE CONVERSION IN GENERAL CODING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING DECODING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS
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Beschreibung
Zusammenfassung:	Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.