Testing operations for memory systems

Methods, systems, and devices for testing operations for memory systems are described. A memory system may include a first circuit and a second circuit configured to test one or more counters tracking the quantity of activates to respective rows of memory cells. In some examples, the memory system may initiate an operation to validate a counter of the memory system. The first circuit may determine if a value of the counter is correct by comparing a set of counter bits representing the value of the counter to a set of parity bits. Subsequently, the second circuit may determine if the counter is incrementing correctly in accordance with a set quantity of activates to the corresponding row of memory cells. If the first circuit or the second circuit detect an error associated with the counter, the memory system may discard the row of memory cells associated with the faulty counter.