Memory page manager

Techniques are disclosed relating to managing page pools for sets of processing work. In some embodiments, a processor assigns sets of processing work to respective primary slots. Page manager circuitry may maintain, in a memory, page pool descriptor information for memory pages allocated to multiple different page pools, maintain a mapping of multiple primary slots of the processor circuitry to a first page pool of the page pools, and cache page pool descriptor entries in the page pool descriptor cache. The page manager circuitry may provide pages to requesting client circuitry from the first page pool for the multiple mapped primary slots. In some embodiments, the page manager circuitry pre-fetches virtual pages. The page manager circuitry may include primary and distribute components.