Techniques for reading memory cells in a memory device during a multi-pass programming operation
The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data state...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Wan, Jun Wan, Zhenni Lei, Bo Xu, Huiwen Agrawal, Nidhi |
description | The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US12057169B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US12057169B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US12057169B23</originalsourceid><addsrcrecordid>eNqNir0KwkAQBtNYiPoO6wMETESDraLYG-u4XL7Eg_tz7yL49hrQ3mpgZqbZrYa6O_0YEKnzQgJutevJwnp5kYIxkbQj_pkWT61A7SDj9tGDSToPHCMF8b2wtWPwAcJJezfPJh2biMWXs2x5OtaHc47gG8TACg6puV6KcrWpiu1uX67_ed7S5z2t</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Techniques for reading memory cells in a memory device during a multi-pass programming operation</title><source>esp@cenet</source><creator>Wan, Jun ; Wan, Zhenni ; Lei, Bo ; Xu, Huiwen ; Agrawal, Nidhi</creator><creatorcontrib>Wan, Jun ; Wan, Zhenni ; Lei, Bo ; Xu, Huiwen ; Agrawal, Nidhi</creatorcontrib><description>The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.</description><language>eng</language><subject>ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240806&DB=EPODOC&CC=US&NR=12057169B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240806&DB=EPODOC&CC=US&NR=12057169B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Wan, Jun</creatorcontrib><creatorcontrib>Wan, Zhenni</creatorcontrib><creatorcontrib>Lei, Bo</creatorcontrib><creatorcontrib>Xu, Huiwen</creatorcontrib><creatorcontrib>Agrawal, Nidhi</creatorcontrib><title>Techniques for reading memory cells in a memory device during a multi-pass programming operation</title><description>The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.</description><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNir0KwkAQBtNYiPoO6wMETESDraLYG-u4XL7Eg_tz7yL49hrQ3mpgZqbZrYa6O_0YEKnzQgJutevJwnp5kYIxkbQj_pkWT61A7SDj9tGDSToPHCMF8b2wtWPwAcJJezfPJh2biMWXs2x5OtaHc47gG8TACg6puV6KcrWpiu1uX67_ed7S5z2t</recordid><startdate>20240806</startdate><enddate>20240806</enddate><creator>Wan, Jun</creator><creator>Wan, Zhenni</creator><creator>Lei, Bo</creator><creator>Xu, Huiwen</creator><creator>Agrawal, Nidhi</creator><scope>EVB</scope></search><sort><creationdate>20240806</creationdate><title>Techniques for reading memory cells in a memory device during a multi-pass programming operation</title><author>Wan, Jun ; Wan, Zhenni ; Lei, Bo ; Xu, Huiwen ; Agrawal, Nidhi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12057169B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Wan, Jun</creatorcontrib><creatorcontrib>Wan, Zhenni</creatorcontrib><creatorcontrib>Lei, Bo</creatorcontrib><creatorcontrib>Xu, Huiwen</creatorcontrib><creatorcontrib>Agrawal, Nidhi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wan, Jun</au><au>Wan, Zhenni</au><au>Lei, Bo</au><au>Xu, Huiwen</au><au>Agrawal, Nidhi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Techniques for reading memory cells in a memory device during a multi-pass programming operation</title><date>2024-08-06</date><risdate>2024</risdate><abstract>The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US12057169B2 |
source | esp@cenet |
subjects | ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES |
title | Techniques for reading memory cells in a memory device during a multi-pass programming operation |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T01%3A31%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Wan,%20Jun&rft.date=2024-08-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS12057169B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |