Logic cell layout design for high density transistors

The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous a...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Ichihashi, Motoi, Zhu, Xuelian, Strehlow, Elizabeth, Mazza, James P, Zeng, Jia
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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