Logic cell layout design for high density transistors

Logic cell layout design for high density transistors

The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous a...

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Hauptverfasser: Ichihashi, Motoi, Zhu, Xuelian, Strehlow, Elizabeth, Mazza, James P, Zeng, Jia
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Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator Ichihashi, Motoi
Zhu, Xuelian
Strehlow, Elizabeth
Mazza, James P
Zeng, Jia
description The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US12046651B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US12046651B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US12046651B23</originalsourceid><addsrcrecordid>eNrjZDD1yU_PTFZITs3JUchJrMwvLVFISS3OTM9TSMsvUsjITM8A8vOKM0sqFUqKEoGM4pL8omIeBta0xJziVF4ozc2g6OYa4uyhm1qQH59aXJCYnJqXWhIfGmxoZGBiZmZq6GRkTIwaAHCvLXs</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Logic cell layout design for high density transistors</title><source>esp@cenet</source><creator>Ichihashi, Motoi ; Zhu, Xuelian ; Strehlow, Elizabeth ; Mazza, James P ; Zeng, Jia</creator><creatorcontrib>Ichihashi, Motoi ; Zhu, Xuelian ; Strehlow, Elizabeth ; Mazza, James P ; Zeng, Jia</creatorcontrib><description>The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240723&amp;DB=EPODOC&amp;CC=US&amp;NR=12046651B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240723&amp;DB=EPODOC&amp;CC=US&amp;NR=12046651B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ichihashi, Motoi</creatorcontrib><creatorcontrib>Zhu, Xuelian</creatorcontrib><creatorcontrib>Strehlow, Elizabeth</creatorcontrib><creatorcontrib>Mazza, James P</creatorcontrib><creatorcontrib>Zeng, Jia</creatorcontrib><title>Logic cell layout design for high density transistors</title><description>The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD1yU_PTFZITs3JUchJrMwvLVFISS3OTM9TSMsvUsjITM8A8vOKM0sqFUqKEoGM4pL8omIeBta0xJziVF4ozc2g6OYa4uyhm1qQH59aXJCYnJqXWhIfGmxoZGBiZmZq6GRkTIwaAHCvLXs</recordid><startdate>20240723</startdate><enddate>20240723</enddate><creator>Ichihashi, Motoi</creator><creator>Zhu, Xuelian</creator><creator>Strehlow, Elizabeth</creator><creator>Mazza, James P</creator><creator>Zeng, Jia</creator><scope>EVB</scope></search><sort><creationdate>20240723</creationdate><title>Logic cell layout design for high density transistors</title><author>Ichihashi, Motoi ; Zhu, Xuelian ; Strehlow, Elizabeth ; Mazza, James P ; Zeng, Jia</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12046651B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Ichihashi, Motoi</creatorcontrib><creatorcontrib>Zhu, Xuelian</creatorcontrib><creatorcontrib>Strehlow, Elizabeth</creatorcontrib><creatorcontrib>Mazza, James P</creatorcontrib><creatorcontrib>Zeng, Jia</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ichihashi, Motoi</au><au>Zhu, Xuelian</au><au>Strehlow, Elizabeth</au><au>Mazza, James P</au><au>Zeng, Jia</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Logic cell layout design for high density transistors</title><date>2024-07-23</date><risdate>2024</risdate><abstract>The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Logic cell layout design for high density transistors
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T15%3A52%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Ichihashi,%20Motoi&rft.date=2024-07-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS12046651B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true