Arrayed element design for chip fuse
A chip fuse includes a first terminal disposed on a first end of a fuse element array and a second terminal disposed on a second end of the fuse element array opposite the first end. The fuse element array includes multiple layers disposed in a stacked arrangement, each layer including a first termi...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A chip fuse includes a first terminal disposed on a first end of a fuse element array and a second terminal disposed on a second end of the fuse element array opposite the first end. The fuse element array includes multiple layers disposed in a stacked arrangement, each layer including a first terminal portion disposed within the first terminal, a second terminal portion disposed within the second terminal, a first fuse element portion orthogonal to and extending between the first terminal portion and the second terminal portion, and a second fuse element portion orthogonal to and extending between the first terminal portion and the second terminal portion. The first fuse element portion is adjacent the second fuse element portion. |
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