Method and system for wafer-level testing

The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Kuo, Yung-Liang, Lin, Wei-Hsun, He, Jun, Lin, Yu-Ting, Lu, Yinlung
Format: Patent
Sprache:eng
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