Data storage devices and related methods to secure host memory buffers with low latency

Aspects of the present disclosure generally relate to data storage devices and related methods that use secure host memory buffers and low latency operations. In one aspect, a controller of a data storage device that is coupled to one or more memory devices is configured to fetch a command from a host device, and fetch entry data from a host memory buffer (HMB) of the host device in response to the command from the host device. In one embodiment, the entry data includes a logical to physical (L2P) address. The controller is also configured to fetch read data from the one or more memory devices using the entry data, conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices, and transmit validity result data to the host device.