Hybrid parallel programming of single-level cell memory

A memory device includes a page buffer with a cache register and data registers, a memory array with a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic. The control logic performs operations including: causing a first page of SLC data to be stored in the cache register; causing the first page of the SLC data to be moved from the cache register to a first data register; causing a subsequent page of the SLC data to be stored in the cache register; causing the SLC data stored in the cache register and in the data registers to be concurrently programmed to the set of sub-blocks, where the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block; and causing a subset of the operations for programming the set of sub-blocks to be performed in parallel.