Clock driver for time-interleaved digital-to-analog converter

In certain aspects, a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal, and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal using the first divided clock signal to generate the first drive clock signal, and inputting the first drive clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal using the second divided clock signal to generate the second drive clock signal, and inputting the second drive clock signal to a clock input of the second sub-DAC.