Pre-decoder circuity

The disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuitry to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. The bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. The pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.