High-speed and low-power successive approximation register analog-to-digital converter (SAR ADC) and analog-to-digital conversion method

The present disclosure relates to a high-speed and low-power successive approximation register analog-to-digital converter (SAR ADC) and an analog-to-digital conversion method. Binary redundancy reassembly is performed to improve a digital-to-analog converter (DAC) capacitor array included in the SAR ADC such that the total number of capacitors included in a capacitor sub-array of the DAC capacitor array is greater than the number of precision bits of the SAR ADC, and the total number of unit capacitors included in all capacitors when the total number of capacitors included in the capacitor sub-array is greater than the number of precision bits of the SAR ADC is equal to the total number of unit capacitors included in all capacitors when the total number of capacitors included in the capacitor sub-array is equal to the number of precision bits of the SAR ADC.