Analysis of events in an integrated circuit using cause tree and buffer

An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.