Configurable routing in a multi-chip system

A first configurable address decoder can be coupled between a source node and a first interconnect fabric, and a second address decoder can be coupled between the first interconnect fabric and a second interconnect fabric. The first address decoder can be configured with a first address mapping tabl...

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Bibliographische Detailangaben
Hauptverfasser:	Izenberg, Erez, Shapira, Yaniv, Nakibly, Guy, Saad, Dan
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	A first configurable address decoder can be coupled between a source node and a first interconnect fabric, and a second address decoder can be coupled between the first interconnect fabric and a second interconnect fabric. The first address decoder can be configured with a first address mapping table that can map a first set of address ranges to a first set of target nodes connected to the first interconnect fabric. The second address decoder can be configured with a second address mapping table that can map a second set of address ranges to a second set of target nodes connected to the second interconnect fabric. The second address decoder can be part of the first set of target nodes. The first address decoder and the second address decoder can be configured or re-configured to determine different routes for a transaction from the source node to a target node in the second set of target nodes via the first and second interconnect fabrics.