BEOL fat wire level ground rule compatible embedded artificial intelligence integration

BEOL fat wire level ground rule compatible embedded artificial intelligence integration

Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface...

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Bibliographische Detailangaben
Hauptverfasser: Narayanan, Vijay, Seo, Soon-Cheon, Kong, Dexin, Saraf, Iqbal Rashid, Jamison, Paul Charles, Kim, Youngseok, Ando, Takashi, Saulnier, Nicole, Miyazoe, Hiroyuki
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.