Terminal resistance circuit, chip and chip communication device

A terminal resistance circuit, a chip and a chip communication device are provided. The terminal resistance circuit can be used for a high-speed differential I/O pair and includes two resistance circuits and a control circuit. An end of the two resistance circuits connected in series is connected to a first interface and another end is connected to a second interface. A conductor wire connected between the two resistance circuits has a target node thereon. The two resistance circuits are symmetrically arranged relative to the target node. The control circuit is connected to the two resistance circuits individually and used to control the two resistance circuits each to be in a turn-off state during powering-on of the chip. An abnormal operation caused by a short circuit between two interfaces of a I/O pair during the powering-on of the chip is avoided and the working stability of the chip is improved.