Integrated circuit layout generation method

A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across th...

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Bibliographische Detailangaben
Hauptverfasser:	Lu, Kuopei, Kuo, Keng-Hua, Ho, Jon-Hsu, Wu, Ze-Ming, Hsieh, Wen-Hsing, Su, Ke-Ying, Su, Ke-Wei, Chang, Lester, Chen, Liang-Yi, Lai, Wen-Koi
Format:	Patent
Sprache:	eng
Schlagworte:	APPARATUS SPECIALLY ADAPTED THEREFOR CALCULATING CINEMATOGRAPHY COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTROGRAPHY HOLOGRAPHY MATERIALS THEREFOR ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS
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Beschreibung
Zusammenfassung:	A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.