Clock oscillator control circuit

A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.