Discrete-time offset correction circuit embedded in a residue amplifier in a pipelined analog-to-digital converter (ADC)

A multi-stage pipelined Analog-to-Digital Converter (ADC) has an offset correction circuit embedded in the residue amplifier between stages. The offset corrector has a low-pass filter that filters the output of the residue amplifier, and the filtered offset is amplified and stored on an offset capacitor during an autozeroing phase of the residue amplifier. During an amplify phase of the residue amplifier, switches disconnect the amplifier from the offset capacitor and instead ground the input of the offset capacitor, and other switches connect the output terminal of the offset capacitor to the input of the residue amplifier. The offset stored on the offset capacitor is combined with the residue voltage from the first ADC stage's capacitor array and applied to an input of the residue amplifier to effectively subtract the detected offset. Two offset capacitors and sets of switches can be used to implement a differential offset corrector.