Page buffer including latches and memory device including the page buffer

The memory device includes a page buffer circuit including a page buffer connected to each of a plurality of bit lines. The page buffer includes at least one additional latch and N number of data latches, and a control logic circuit that controls a setting of the page buffer. Based on a first setting, data programmed in a current program operation is stored in some of the N data latches and the at least one additional latch, and data which is to be programmed in a next program operation before the current program operation is completed is stored in some other of the N data latches and the at least one additional latches. Based on a second setting, externally provided data is not stored in the at least one additional latch in the current program operation and the next program operation.