Memories for calibrating sensing of memory cell data states

Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a particular voltage level in response to each respective plurality of first logic levels for the plurality of sense circuits and their respective plurality of voltage levels, and to determine, for each sense circuit of the plurality of sense circuits, a respective second logic level for that sense circuit while capacitively coupling the particular voltage level to its respective sense node.