High-level synthesis (HLS) method and apparatus to specify parallelism in computer hardware

High-level synthesis (HLS) method and apparatus to specify parallelism in computer hardware

A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving a multi-threaded software program with at least one C++ thread; generating a register-transfer level (RTL) hardware description of the at least one C++ thread; and automatically inferring gen...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Choi, Jongsok, Soliman, Muhammad R, Anderson, Jason Helge, Lian, Ruolong, Canis, Andrew Christopher
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving a multi-threaded software program with at least one C++ thread; generating a register-transfer level (RTL) hardware description of the at least one C++ thread; and automatically inferring generation of parallel hardware RTL in response to receiving the at least one C++ thread.