3D quilt memory array for FeRAM and DRAM

Methods, systems, and devices for memory array with multiplexed select lines are described. In some cases, a memory cell of the memory device may include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a selection line to selectively couple the memory cell with a digit line. The selection line may be provided in parallel to each digit line for multiplexing the digit lines toward a sense amplifier while a plurality of drivers, one for each selection line, may be provided in a staggered configuration under the memory array and split in even drivers and odd drivers for corresponding adjacent tiles of the memory array.