Memory system and data processing system including multi-core controller for classified commands

A controller for controlling a memory devices is provided to include: a first core configured to control first memory dies; a second core configured to control second memory dies; and a host interface configured to: receive submission queue tail pointers and command information on each of commands corresponding to the tail pointers from host, classify the commands into a first address command associated with a first logical address and a second address command associated with a second logical address based on the command information, fetch the first and second address commands from host, and provide the first address command to the first core and the second address command to the second core based on the processing order of the first and second address commands determined based on status of the first memory dies and the second memory dies.