3D DRAM structure with high mobility channel

Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capa...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Kitajima, Tomohiko, Kang, Sung-Kwan, Kang, Chang Seok, Natarajan, Sanjay, Lee, Gill Yong, Liu, Lequn
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	Kitajima, Tomohiko Kang, Sung-Kwan Kang, Chang Seok Natarajan, Sanjay Lee, Gill Yong Liu, Lequn
description	Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11749315B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11749315B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11749315B23</originalsourceid><addsrcrecordid>eNrjZNAxdlFwCXL0VSguKSpNLiktSlUozyzJUMjITM9QyM1PyszJLKlUSM5IzMtLzeFhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaG5iaWxoamTkbGxKgBADC7KS8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>3D DRAM structure with high mobility channel</title><source>esp@cenet</source><creator>Kitajima, Tomohiko ; Kang, Sung-Kwan ; Kang, Chang Seok ; Natarajan, Sanjay ; Lee, Gill Yong ; Liu, Lequn</creator><creatorcontrib>Kitajima, Tomohiko ; Kang, Sung-Kwan ; Kang, Chang Seok ; Natarajan, Sanjay ; Lee, Gill Yong ; Liu, Lequn</creatorcontrib><description>Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.</description><language>eng</language><subject>ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230905&DB=EPODOC&CC=US&NR=11749315B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230905&DB=EPODOC&CC=US&NR=11749315B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kitajima, Tomohiko</creatorcontrib><creatorcontrib>Kang, Sung-Kwan</creatorcontrib><creatorcontrib>Kang, Chang Seok</creatorcontrib><creatorcontrib>Natarajan, Sanjay</creatorcontrib><creatorcontrib>Lee, Gill Yong</creatorcontrib><creatorcontrib>Liu, Lequn</creatorcontrib><title>3D DRAM structure with high mobility channel</title><description>Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.</description><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAxdlFwCXL0VSguKSpNLiktSlUozyzJUMjITM9QyM1PyszJLKlUSM5IzMtLzeFhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaG5iaWxoamTkbGxKgBADC7KS8</recordid><startdate>20230905</startdate><enddate>20230905</enddate><creator>Kitajima, Tomohiko</creator><creator>Kang, Sung-Kwan</creator><creator>Kang, Chang Seok</creator><creator>Natarajan, Sanjay</creator><creator>Lee, Gill Yong</creator><creator>Liu, Lequn</creator><scope>EVB</scope></search><sort><creationdate>20230905</creationdate><title>3D DRAM structure with high mobility channel</title><author>Kitajima, Tomohiko ; Kang, Sung-Kwan ; Kang, Chang Seok ; Natarajan, Sanjay ; Lee, Gill Yong ; Liu, Lequn</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11749315B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Kitajima, Tomohiko</creatorcontrib><creatorcontrib>Kang, Sung-Kwan</creatorcontrib><creatorcontrib>Kang, Chang Seok</creatorcontrib><creatorcontrib>Natarajan, Sanjay</creatorcontrib><creatorcontrib>Lee, Gill Yong</creatorcontrib><creatorcontrib>Liu, Lequn</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kitajima, Tomohiko</au><au>Kang, Sung-Kwan</au><au>Kang, Chang Seok</au><au>Natarajan, Sanjay</au><au>Lee, Gill Yong</au><au>Liu, Lequn</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>3D DRAM structure with high mobility channel</title><date>2023-09-05</date><risdate>2023</risdate><abstract>Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US11749315B2
source	esp@cenet
subjects	ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
title	3D DRAM structure with high mobility channel
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-16T21%3A36%3A16IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kitajima,%20Tomohiko&rft.date=2023-09-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11749315B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true