Common bus data flow for serially chained devices

In described examples, a circuit includes a system bus controller having a first downstream port and is configured to generate a first downstream frame responsive to a first local bus transmission received by a first local bus controller, and to generate a second downstream frame responsive to a sec...

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Bibliographische Detailangaben
Hauptverfasser:	Prayogo, Justin, Parekh, Sinjeet, Liu, Xin, Ceekala, Vijaya
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	In described examples, a circuit includes a system bus controller having a first downstream port and is configured to generate a first downstream frame responsive to a first local bus transmission received by a first local bus controller, and to generate a second downstream frame responsive to a second local bus transmission received by a second local bus controller. The system bus controller is configured to generate a downstream aggregate frame responsive to the first downstream frame and the second downstream frame and is configured to initiate transmission of the downstream aggregate frame at the first downstream port. The system bus controller is adapted to receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame and is configured to generate a first upstream transmission responsive to the first upstream frame and to generate the second upstream transmission responsive to the second upstream frame.