Arbitration control for pseudostatic random access memory device

An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a first arbiter circuit and a second arbiter circuit. The first arbiter circuit receives a normal access request signal and a refresh access request signal and generates a first output signal in response to a logical operation to arbitrate between the normal access reqeuest signal and the refresh access request signal. The second arbiter circuit configured to receive the first output signal and a delayed signal of the first output signal, and to generate a second output signal in response to a logical operation of the first output signal and the delayed signal. The second output signal has a first logical state indicative of granting the read or write access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.