Memory system with burst mode having logic gates as sense elements

Memory systems with burst mode having logic gates as sense elements and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first wordline, a second set of memory cells coupled to a second wordline, and a plurality of sense elements, not including any sense amplifiers. The control unit is configured to generate control signals for: in response to a burst mode read request, simultaneously: (1) asserting a first wordline signal on the first wordline coupled to each of a plurality of first set of bitlines, and (2) asserting a second wordline signal on the second wordline coupled to each of a plurality of second set of bitlines, and as part of a burst, outputting data corresponding to a subset of each of the first set of memory cells and the second set of memory cells.