Integrated circuit stack verification method and system for performing the same

A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer locatio...

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Bibliographische Detailangaben
Hauptverfasser: Huang, Chin-Yuan, Lin, Kai-Yun, Jou, Chewn-Pu, Chen, Shuo-Mao, Kuo, Feng Wei, Chen, Ho-Hsiang
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.