System and method for mitigating effect of erase cells on adjacent cells

Methods and systems for increasing reliability of a data storage device are disclosed. During fabrication runs of a non-volatile memory (NVM) die, such as a NAND, there may be a number of memory cells designated as erase cells. When one or more erase cells are physically adjacent to programmed memory cell, electrical effects of the erase cell may cause a bit to flip in the adjacent good memory cell. To mitigate this effect, an LDPC engine is used to generate additional parity bits for the erased bit/cells. When a host requests data from the NVM, the parity bits may be used to correct additional errors because of the erased state to programmed state bit flips.