Apparatus and method

Apparatus comprises two or more processing devices each having an associated translation lookaside buffer to store translation data defining address translations between virtual and physical memory addresses, each address translation being associated with a respective virtual address space; and cont...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Vougioukas, Ilias, Nikoleris, Nikos, Sandberg, Andreas Lars, Diestelhorst, Stephan
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Apparatus comprises two or more processing devices each having an associated translation lookaside buffer to store translation data defining address translations between virtual and physical memory addresses, each address translation being associated with a respective virtual address space; and control circuitry to control the transfer of at least a subset of the translation data from the translation lookaside buffer associated with a first processing device to the translation lookaside buffer associated with a second, different, processing device.