Intermediate separation layers at the back-end-of-line

Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD lay...

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Bibliographische Detailangaben
Hauptverfasser:	Lajoie, Travis W, George, Gregory, Ogadhoh, Shem, Le, Van H, Chen, Ting, Ghani, Tahir, Gardiner, Allen B, Ku, Chieh-Jen, Hadagali, Vinaykumar V, Wang, Pei-Hua, Hamzaoglu, Fatih, Alzate Vinasco, Juan G, Sell, Bernhard, Arslan, Umut, Mehta, Nikhil, Sharma, Abhishek A, Garg, Akash, Rollins, Julie, Kavalieros, Jack T
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.