Integrated circuit with capability of inhibiting ESD zap
An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected betwe...
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| creator | Hsu, Hsin-Kun Lai, Chih-Wei Wu, Yi-Han Lin, Kun-Hsin Ting, Yun-Jen |
| description | An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node. |
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An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. 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A gate terminal of the switching transistor is connected with the fifth node.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS</subject><subject>GENERATION</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDwzCtJTS9KLElNUUjOLEouzSxRKM8syVBITixITMrMySypVMhPU8jMy8hMyizJzEtXcA12UahKLOBhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaGZoZmxmYGTkbGxKgBAPfALhw</recordid><startdate>20230328</startdate><enddate>20230328</enddate><creator>Hsu, Hsin-Kun</creator><creator>Lai, Chih-Wei</creator><creator>Wu, Yi-Han</creator><creator>Lin, Kun-Hsin</creator><creator>Ting, Yun-Jen</creator><scope>EVB</scope></search><sort><creationdate>20230328</creationdate><title>Integrated circuit with capability of inhibiting ESD zap</title><author>Hsu, Hsin-Kun ; Lai, Chih-Wei ; Wu, Yi-Han ; Lin, Kun-Hsin ; Ting, Yun-Jen</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11616360B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS</topic><topic>GENERATION</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Hsu, Hsin-Kun</creatorcontrib><creatorcontrib>Lai, Chih-Wei</creatorcontrib><creatorcontrib>Wu, Yi-Han</creatorcontrib><creatorcontrib>Lin, Kun-Hsin</creatorcontrib><creatorcontrib>Ting, Yun-Jen</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hsu, Hsin-Kun</au><au>Lai, Chih-Wei</au><au>Wu, Yi-Han</au><au>Lin, Kun-Hsin</au><au>Ting, Yun-Jen</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit with capability of inhibiting ESD zap</title><date>2023-03-28</date><risdate>2023</risdate><abstract>An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS GENERATION SEMICONDUCTOR DEVICES |
| title | Integrated circuit with capability of inhibiting ESD zap |
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