Integrated circuit with capability of inhibiting ESD zap

Integrated circuit with capability of inhibiting ESD zap

An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected betwe...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Hsu, Hsin-Kun, Lai, Chih-Wei, Wu, Yi-Han, Lin, Kun-Hsin, Ting, Yun-Jen
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
GENERATION
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node.