Comparator architecture for reduced delay and lower static current
Described embodiments include a comparator circuit comprising an input voltage terminal, a reference voltage terminal, and a rising edge decode circuit having inputs coupled to the input voltage terminal and the reference voltage terminal. The rising edge output provides a rising edge decode signal...
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| creator | Tadeparthy, Preetam Charan Anand Jaladanki, Vishnuvardhan Reddy |
| description | Described embodiments include a comparator circuit comprising an input voltage terminal, a reference voltage terminal, and a rising edge decode circuit having inputs coupled to the input voltage terminal and the reference voltage terminal. The rising edge output provides a rising edge decode signal indicating the input signal transitioned from being smaller than the reference voltage signal to being larger than the reference voltage signal. A falling edge decode circuit has inputs coupled to the input voltage terminal and the reference voltage terminal, and a falling edge output providing a falling edge decode signal indicating that the input signal transitioned from being larger than the reference voltage signal to being smaller than the reference voltage signal. Also, a decode logic circuit provides a comparator output in response to the rising edge decode signal and the falling edge decode signal. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11595033B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11595033B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11595033B23</originalsourceid><addsrcrecordid>eNqNyjEKAjEQRuFtLES9w3gAwTVsYbuLYq_WyzD5FxdiEiYTxNtr4QGsHny8ZdMP6ZlZ2ZISqzxmg1hV0PQFha8CTx6B38TRU0gvKBVjm4WkqiLaullMHAo2v66a7fl0Gy475DSiZBZE2Hi_tm137PbO9Qf3z_MBbz4yhw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Comparator architecture for reduced delay and lower static current</title><source>esp@cenet</source><creator>Tadeparthy, Preetam Charan Anand ; Jaladanki, Vishnuvardhan Reddy</creator><creatorcontrib>Tadeparthy, Preetam Charan Anand ; Jaladanki, Vishnuvardhan Reddy</creatorcontrib><description>Described embodiments include a comparator circuit comprising an input voltage terminal, a reference voltage terminal, and a rising edge decode circuit having inputs coupled to the input voltage terminal and the reference voltage terminal. The rising edge output provides a rising edge decode signal indicating the input signal transitioned from being smaller than the reference voltage signal to being larger than the reference voltage signal. A falling edge decode circuit has inputs coupled to the input voltage terminal and the reference voltage terminal, and a falling edge output providing a falling edge decode signal indicating that the input signal transitioned from being larger than the reference voltage signal to being smaller than the reference voltage signal. Also, a decode logic circuit provides a comparator output in response to the rising edge decode signal and the falling edge decode signal.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230228&DB=EPODOC&CC=US&NR=11595033B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230228&DB=EPODOC&CC=US&NR=11595033B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Tadeparthy, Preetam Charan Anand</creatorcontrib><creatorcontrib>Jaladanki, Vishnuvardhan Reddy</creatorcontrib><title>Comparator architecture for reduced delay and lower static current</title><description>Described embodiments include a comparator circuit comprising an input voltage terminal, a reference voltage terminal, and a rising edge decode circuit having inputs coupled to the input voltage terminal and the reference voltage terminal. The rising edge output provides a rising edge decode signal indicating the input signal transitioned from being smaller than the reference voltage signal to being larger than the reference voltage signal. A falling edge decode circuit has inputs coupled to the input voltage terminal and the reference voltage terminal, and a falling edge output providing a falling edge decode signal indicating that the input signal transitioned from being larger than the reference voltage signal to being smaller than the reference voltage signal. Also, a decode logic circuit provides a comparator output in response to the rising edge decode signal and the falling edge decode signal.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEKAjEQRuFtLES9w3gAwTVsYbuLYq_WyzD5FxdiEiYTxNtr4QGsHny8ZdMP6ZlZ2ZISqzxmg1hV0PQFha8CTx6B38TRU0gvKBVjm4WkqiLaullMHAo2v66a7fl0Gy475DSiZBZE2Hi_tm137PbO9Qf3z_MBbz4yhw</recordid><startdate>20230228</startdate><enddate>20230228</enddate><creator>Tadeparthy, Preetam Charan Anand</creator><creator>Jaladanki, Vishnuvardhan Reddy</creator><scope>EVB</scope></search><sort><creationdate>20230228</creationdate><title>Comparator architecture for reduced delay and lower static current</title><author>Tadeparthy, Preetam Charan Anand ; Jaladanki, Vishnuvardhan Reddy</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11595033B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>Tadeparthy, Preetam Charan Anand</creatorcontrib><creatorcontrib>Jaladanki, Vishnuvardhan Reddy</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tadeparthy, Preetam Charan Anand</au><au>Jaladanki, Vishnuvardhan Reddy</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Comparator architecture for reduced delay and lower static current</title><date>2023-02-28</date><risdate>2023</risdate><abstract>Described embodiments include a comparator circuit comprising an input voltage terminal, a reference voltage terminal, and a rising edge decode circuit having inputs coupled to the input voltage terminal and the reference voltage terminal. The rising edge output provides a rising edge decode signal indicating the input signal transitioned from being smaller than the reference voltage signal to being larger than the reference voltage signal. A falling edge decode circuit has inputs coupled to the input voltage terminal and the reference voltage terminal, and a falling edge output providing a falling edge decode signal indicating that the input signal transitioned from being larger than the reference voltage signal to being smaller than the reference voltage signal. Also, a decode logic circuit provides a comparator output in response to the rising edge decode signal and the falling edge decode signal.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
| title | Comparator architecture for reduced delay and lower static current |
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